library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use std.textio.all;

entity tb_pwm is
end tb_pwm;

architecture structure of tb_pwm is
	component pwm
		port (
		clock: in std_logic;
        reset: in std_logic;
		direction: in std_logic;
		dutycycle: in std_logic_vector(9 downto 0);
		pwm_out: out std_logic;
		direction_out: out std_logic
		);
	end component;
	
    signal direction, direction_out, pwm_out : std_logic;
	signal dutycycle: std_logic_vector(9 downto 0);
    signal clock : std_ulogic := '0';
	signal reset : std_ulogic := '0';
begin
	duv: pwm
		port map (clock=>clock, reset=>reset, direction=>direction,
				dutycycle=>dutycycle, pwm_out=>pwm_out, direction_out=>direction_out);

    clock <= not clock after 1 ns;
	reset <= '0', '1' after 4 ns;
	
	seq: process
	begin
        direction <= '1';
		dutycycle <= "0000000000";
		wait for 2048 ns;
		dutycycle <= "0000100000";
		wait for 2048 ns;
		dutycycle <= "1000000000";
		wait for 2048 ns;
		dutycycle <= "1111111111";
		
		wait;
	end process;
	
end structure;

